Chief Architectural Designer

17 hours ago

Surat, Gujarat, India beBeeSeniorStaffEngineer Full time ₹ 1,80,00,000 - ₹ 2,10,00,000

Job Opportunity

We are seeking a skilled Senior Staff Engineer to lead the development of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, AI accelerators, interconnects, memory architecture, and multi-level caches.

The successful candidate will contribute to and manage a team for the development of architecture, microarchitecture, and design of SoCs including RISC-V, ARM or proprietary processor designs, and high-speed interfaces for off-chip memories.

This position involves leading a project through the entire product development process.

Key Responsibilities:

  • Develop and execute Wireless SoC's from definition, through execution, and into production
  • Define and plan product requirements and provide necessary design collateral
  • Coordinate with cross-functional teams to develop SoC architecture or technical specification to meet product requirements
  • Lead design schedule, including milestones and resource requirements, and coordinate with global design functional leads
  • Represent the design community to provide succinct weekly status and attend cross-functional meetings
  • Maintain design collateral such as documentation, register libraries, and pinouts delivered to cross-functional teams
  • Foster collaboration among team members to achieve first tapeout
  • Support validation and product test teams during silicon bringup, validation, characterization, and qualification
  • Tackle and resolve issues reported during silicon evaluation

Requirements:

  • 12+ years of experience in industry
  • Bachelor or Master's degree in Electrical or Computer Engineering
  • Proven track record of leading complex IP, SOC development projects execution
  • Able to build strong technical teams and drive top-down planning and execution of SOC projects
  • Hands-on experience in full-chip development cycle and knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
  • Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc. and processors like RISC-V and ARM processors
  • Awareness of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints, and STA Timing Closure
  • Experience with DFT including Scan, ATPG, MBIST and low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
  • Proficiency in Verilog and System Verilog and scripting languages like Perl, Python, Tcl, shell

Benefits & Perks:

  • Employee Stock Purchase Plan (ESPP)
  • Insurance plans with Outpatient cover
  • National Pension Scheme (NPS)
  • Flexible work policy
  • Childcare support

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