Senior ASIC Design Engineer
1 week ago
We are seeking a highly skilled Principal Engineer I - ASIC Physical Verification to join our team at Micron Technology. This individual will be responsible for block/chip tile PV closure, DRC & LVS closure, and physical verification convergence.
About Us:
Micron is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. Our vision is to transform how the world uses information to enrich life for everyone.
Responsibilities:
As a Principal Engineer I - ASIC Physical Verification, you will be responsible for:
- Block/Chip Tile PV closure to achieve the best PPA
- DRC & LVS closure for Block and Full Chip for complex hierarchical Designs in 5nm/3nm nodes
- Interaction with IR, IP, ESD & PD teams for Physical Verification Convergence & Resolving Conflicts
- Able to work on multiple blocks at same time with minimal supervision
- Responsible for Full Chip LVS & DRC closure
- Responsible for Analog integration closure for all IP's used in SOC
- Interactions with Foundry team for Full chip Tapeout
Required Skills and Qualifications:
To be successful in this role, you will need:
- 8-14 years of relevant experience in ASIC Physical Verification
- Good understanding of overall design Flow from RTL to GDS
- Hands on Experience on Physical Verification closure of full chip & Hierarchical Designs
- Hands on DRC & LVS Experience on Lower node Technologies with Synopsys/Siemens Tools
- Good knowledge on PnR flow
- Knowledge on Perl / TCL / Python scripting language
- Experience on multi voltage designs
- Good understanding of all Phases of Physical Design (PnR/STA/PV/IR)
What We Offer:
At Micron, we offer a dynamic and challenging work environment with opportunities for professional growth and development.
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