Design Verification Lead

1 day ago


Nagpur, Maharashtra, India beBeeVerification Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

We are seeking a skilled and versatile Senior Design Verification Engineer to join our team. As a key member of our design verification team, you will be responsible for developing and executing test cases and regressions for DSP/Processor subsystems.

You will perform performance analysis for DSP/NPU workloads, collaborate with architecture, design, and software teams, and develop C-based verification flows along with SV/UVM-based environments.

In addition, you will work on coverage closure, regressions, and debug at IP/Subsystem level. You must have strong knowledge of SystemVerilog & UVM, C-based verification experience, and knowledge of DSP architectures / Neural Network Engines (NNE).

You should also have performance verification expertise (latency/throughput) and 4+ years of IP/Sub-system DV experience. If you have hands-on expertise in these areas, we want to hear from you

Responsibilities:
  • Develop and execute test cases and regressions for DSP/Processor subsystems.
  • Perform performance analysis for DSP/NPU workloads.
  • Work on coverage closure, regressions, and debug at IP/Subsystem level.
  • Collaborate with architecture, design, and software teams.
  • Develop C-based verification flows along with SV/UVM-based environments.
Requirements:
  • Strong in SystemVerilog & UVM.
  • C-based verification experience (processors).
  • Knowledge of DSP architectures / Neural Network Engines (NNE).
  • Performance verification expertise (latency/throughput).
  • 4+ years of IP/Sub-system DV experience.
Alternate Job Role: Debug Subsystem

As an alternate role, you will work on end-to-end Debug Subsystem Verification (trace, crash debug, visibility fabric), define and execute Verification Plans (VPlan), and perform RTL DV, GLS, regression automation, and coverage closure.

Collaboration with SW & Architecture teams is necessary for debug feature validation, and you will support ARM CPU debug infrastructure verification (CoreSight). The requirements for this alternate role include strong knowledge of SystemVerilog, UVM, RTL DV, GLS, understanding of ARM CoreSight Debug Architecture, and 4+ years of relevant verification experience.



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