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2 days ago
We are seeking an experienced processor architect to lead the design and development of high-performance interconnects.
- This role is responsible for creating cutting-edge microarchitecture, designing RTL, and collaborating with verification, DFT, physical design, FW, SW teams to deliver the feature.
- The ideal candidate will have a strong understanding of queuing theory, numa/nuca architecture, and proficiency in HDLs - VHDL / Verilog.
The chosen candidate will participate in silicon bring-up and validation of the hardware and ensure pre-silicon design meets all functional, area, and timing goals.
Key Requirements:
- Master's Degree in Computer Science or related field.
- At least 8 years of experience in processor interconnect design delivery leadership.
- Expertise in SMP coherency, on-chip interconnect topologies, snoop and data network protocols.
- Strong understanding of latency and bandwidth requirements.
Preferred Skills:
- Experience with different on-chip interconnect topologies (e.g., mesh, crossbar).
- Proficient in HDLs - VHDL / Verilog.
- Good understanding of Physical Design and collaboration with physical design teams for floor planning, wire layer usage, and budgets.
Benefits:
Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today's market.
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