Design Verification Project Lead
2 days ago
The ideal candidate will be responsible for leading Design Verification projects to ensure timely and high-quality delivery.
A key aspect of this role is defining verification strategies, test plans, coverage goals, and closure metrics in alignment with industry standards.
- Provide technical guidance in SystemVerilog, UVM-based testbench development, coverage closure, debugging, and verification methodologies.
- Collaborate with architects, designers, and DV engineers across global teams to drive seamless execution.
- Manage multi-site DV teams, track progress, and mitigate risks through proactive planning.
- Conduct status reporting, milestone reviews, and client interactions.
- Mentor junior engineers and ensure adherence to best practices in verification and project management.
Required Skills & Experience:
- 14 to 20+ years of experience in Design Verification (IP / Subsystem / SoC level).
- Strong expertise in SystemVerilog, UVM, SVA, and coverage-driven verification.
- Hands-on knowledge of AMBA protocols (AXI, AHB, APB) and Memory/DRAM verification flows.
- Experience with Gate Level Simulation (GLS), Low Power (UPF), and Formal Verification is a strong plus.
- Exposure to EDA tools such as Cadence Xcelium, Synopsys VCS, and Verdi.
- Proven experience in project/program management, leading DV teams (10+ engineers).
- Strong stakeholder management, planning, and execution skills.
- Excellent communication and leadership skills.
Benefits and Perks: The successful candidate will have the opportunity to work with a dynamic team, driving innovative solutions and continuous improvement.
What We Offer: A collaborative and supportive work environment, opportunities for professional growth and development, and a competitive compensation package.
How to Apply: If you are a motivated and experienced professional looking to take your career to the next level, please submit your application, including your resume and cover letter.
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