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Embedded Design Verification Expert

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Job Title:

 

  • Design Verification Specialist

 

About the Role:

This position involves verifying that designed products meet required specifications and standards. The ideal candidate will have hands-on experience in ZD/PAGLS/SDF/Scan dump verification.

 

Key Responsibilities:

  • Develop test plans to ensure designs meet specifications and standards.
  • Collaborate with cross-functional teams to identify and debug issues.
  • Provide expertise in debugging netlist functional failures, low-power awareness verification, timing simulation failures, and setup and hold violation fundamentals.
  • Contribute to developing relevant test plans and scripts using System Verilog, UVM, and other methodologies.
  • Participate in identifying and implementing improvements to the design verification process.

 

Required Skills and Qualifications:

  • Strong Debug, UVM, System Verilog, and Digital Fundamentals skills.
  • GLS hands-on experience in ZD/PAGLS/SDF/Scan dump verification.
  • Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5).
  • Understanding of bus protocols like AHB/AXI/ACE/ACE-Lite.

 

Benefits:

  • Opportunity to work on challenging projects and develop new skills.
  • Collaborative team environment with opportunities for growth and development.