
Lead ASIC Verification Engineer
1 day ago
As a key member of our ASIC development team, you will play a pivotal role in bringing cutting-edge designs to life. Your expertise in physical integration and verification will be instrumental in achieving quality tapeout and first-pass silicon success.
THE PERSON:
A successful candidate will work closely with physical design engineers to deliver full-chip SoC physical integration, verification, and tapeout. The ideal candidate will possess excellent communication and problem-solving skills, as well as the ability to drive multiple projects simultaneously.
KEY RESPONSIBILITIES:
- Drive Full Chip Physical Integration and Verification (DRC/LVS, ERC, DFM checks)
- Collaborate with fab contacts for all tapeout activities leading to final tapeout
- Work Closely with Physical Design Implementation and Signoff Teams to Achieve Faster Time-to-Market
- Develop New Flows and Methodologies in Physical Verification Domain
PREFERRED SKILLSET:
- More than 12 years of relevant experience
- Driven Multiple Tapeouts Across Different Technology Nodes
- Sound Knowledge of Full-Chip Physical Integration and Verification Flows
- Hands-On Experience with Industry-Standard Tools such as Calibre and ICV
- Sound Understanding of DRC/LVS Decks and Ability to Update as Required
- Proficient in Scripting Languages such as Tcl and Perl
- Self-Driven, Positive Attitude, and Team Player
ACADEMIC CREDENTIALS:
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering
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