Senior Verification Specialist

2 weeks ago

Hyderabad, Telangana, India beBeeVerification Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

We are seeking an experienced Verification Engineer to join our team in the development of DDR memory interface designs.

 

Key Responsibilities:
  • We will define and implement verification strategies and test plans for DDR memory interfaces, focusing on thoroughness and reliability.
  • We will develop UVM/SystemVerilog-based testbenches and reusable verification components to enhance efficiency.
  • We will perform protocol-level verification for DDR memory interfaces and validate compliance with industry standards.
  • We will collaborate closely with architecture, RTL, and system teams to ensure design intent and corner cases are well understood.
  • We will own functional coverage, regression setup, and closure to guarantee comprehensive verification.
  • We will integrate DDR models, controllers, PHYs, and validate their interactions to ensure seamless functionality.
  • We will debug and resolve simulation failures and functional issues promptly and effectively.
  • We will drive code and functional coverage improvements to ensure thorough verification and high-quality results.
  • We will lead or participate in technical reviews and mentor junior engineers to foster growth and expertise.
Required Skills and Qualifications:
  • Mandatory 10+ years of hands-on experience in ASIC/IP/SoC verification with a proven track record of success.
  • Strong expertise in SystemVerilog, UVM, and functional coverage methodology is essential.
  • In-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocols is crucial.
  • Experience with DDR controllers, PHY integration, and JEDEC standards is necessary.
  • Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc.
  • Good scripting skills in Python, Perl, or Shell for automation and regression management are required.
  • Excellent debugging and problem-solving skills are essential.
  • Familiarity with AXI/AHB protocols and interconnects is a plus.
  • Experience working with memory models and timing analysis is beneficial.
Preferred Qualifications:
  • Experience with post-silicon validation or DDR hardware bring-up is desirable.
  • Knowledge of formal verification tools and techniques is a plus.
  • Experience with low power verification and timing closure tools is beneficial.

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