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Design Verification Expert

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Bengaluru, Karnataka, India beBeeVerification Full time ₹ 1,20,00,000 - ₹ 1,80,00,000
Job Opportunity: Senior Design Verification Engineer

We are seeking a seasoned Senior Design Verification Engineer with expertise in StemVerilog/UVM methodology and/or C/C++ based verification. The ideal candidate will have 5+ years of hands-on experience in developing functional tests, driving design verification to closure, and debugging functional failures.

  • The successful candidate will be responsible for defining and implementing IP/SoC verification plans, building verification test benches, and architecting and implementing design verification infrastructure.
  • They will also develop and execute the full verification cycle, partner with the design team to resolve functional failures, and ensure high-quality design delivery.

Key Requirements:

  • Bachelor's or Master's degree in Computer Science, Electronics Engineering, or equivalent practical experience.
  • 5+ years of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification.
  • Expertise in development of UVM based verification environments from scratch, architecting and implementing design verification infrastructure, and executing the full verification cycle.
  • Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs, IP or integration verification, and protocols like AMBA, PCIe, DDR, USB, Ethernet.
  • Proficiency in E tools and scripting languages (Python, TCL, Perl, Shell) used to build tools and flows for verification environments, as well as revision control systems like Mercurial(Hg), Git, or SVN.

Preferred Qualifications:

  • Mastery of UVM based verification environments, design verification infrastructure, and full verification cycles.
  • Strong understanding of IP or integration verification, including protocols like AMBA, PCIe, DDR, USB, Ethernet.
  • Experience with ARM/RISC-V based CPU sub-stems or SoCs, and strong problem-solving skills.