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Senior IC Designer
2 weeks ago
Job Opportunity: Experienced RTL to GDSII Engineers with a strong technical expertise in synthesis and timing analysis are required for key roles in Bangalore.
Key Responsibilities:- Develop and maintain Design Compiler (DC) constraint files.
- Perform Pre-Timing Synthesis on RTL designs.
- Execute Pre-Static Timing Analysis (Pre-STA) and support Physical Design (PD) activities.
- Collaborate with cross-functional teams to achieve design closure and ensure high-quality deliverables.
The ideal candidate should have 5+ years of experience in RTL to GDSII design flow, a strong background in synthesis, STA, and physical design processes, as well as hands-on expertise in writing DC constraint files and proven ability to debug and resolve design and timing issues.
