Senior Electrical Validation Engineer

3 weeks ago


Bengaluru, Karnataka, India Cadence Design Systems, Inc. Full time
Job Title:

Design Engineering Manager

Cadence Design Systems, Inc. is a pioneering leader in electronic design, leveraging its expertise in computational software to deliver software, hardware, and IP that turn design concepts into reality.

As a Design Engineering Manager, you will play a pivotal role in leading the Pre-Silicon Physical Layer Electrical Validation infrastructure development and post-silicon validation efforts for Cadence's High Speed SERDES Test chips.

Key Responsibilities:

  • Designing hardware and software architecture for test chip validation
  • Defining test plans for rigorous Physical Layer Electrical specifications compliance testing
  • Implementing tests and generating high-quality test reports based on results

Requirements:

  • 6-10 years (Btech) or 4-8 years (Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
  • Deep Physical Layer electrical validation experience on High Speed SERDES protocols like PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO
  • Strong hands-on experience with lab equipment like Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT)

Preferred Qualifications:

  • Experience managing small teams (at least 2 members)
  • Experience leading complete post-silicon validation efforts for at least one full project
  • 1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping

Cadence offers a unique culture that promotes collaboration and employee development, with a focus on physical and mental well-being, career growth, and recognition of employee achievements.



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