Chief Digital Architect
4 days ago
We are seeking a highly skilled and motivated Chip Lead with 15+ years of experience to own the overall chip architecture and design execution.
The ideal candidate will lead multi-block design integration, manage handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT.
A strong background in digital IC design (RTL to GDSII), system-level architecture and IP integration, timing closure (STA) and power-performance-area (PPA) optimization, UPF/CPF for low-power design, and familiarity with design for manufacturability, test (DFT), and silicon debug is required.
Required Skills and Qualifications:- Bachelor's degree in Electrical Engineering, Electronics, or Computer Engineering.
- Mastery of digital IC design from RTL to GDSII.
- Expertise in system-level architecture and IP integration.
- Proven ability in timing closure and power-performance-area optimization.
- Familiarity with low-power design using UPF/CPF.
- Knowledge of design for manufacturability, test, and silicon debug.
- Own the overall chip architecture and design execution.
- Lead multi-block design integration.
- Manage handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT.
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