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24 hours ago
We are seeking a seasoned expert to lead complex subsystems in static timing analysis and place and route activities. This role requires strong technical expertise, excellent leadership skills, and the ability to drive automation and validation across subsystem boundaries.
Key Responsibilities:- Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
- Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
- Drive automation and validation of timing and physical design data across subsystem boundaries.
- Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
- Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
- 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).
- Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
- Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
- Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
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