Chief Verification Engineer for Analog Mixed-Signal Systems

18 hours ago

Bareilly, Uttar Pradesh, India beBeeVerification Full time ₹ 20,00,000 - ₹ 25,00,000
Job Opportunity

We are seeking a highly skilled verification engineer to develop and execute comprehensive AMS verification strategies for analog/mixed-signal IPs and SoCs.

  • Create and implement verification plans, including testbenches, stimulus generation, and checking strategies.
  • Design and maintain SystemVerilog, Verilog-AMS, or UVM-based verification environments.
  • Perform co-simulation of analog/digital designs using industry tools.
  • Conduct mixed-signal simulations, behavioral modeling of analog blocks, and integration into top-level environments.
  • Collaborate with analog designers to create AMS behavioral models for early integration and verification.
  • Debug complex AMS simulation issues across multiple abstraction levels.
  • Drive coverage analysis and sign-off using functional, formal, and assertion-based methods.
  • Mentor junior engineers in best practices and methodologies.

Responsibilities:

  • Ensure verification deliverables meet project timelines and quality standards.

Requirements:

  • Minimum 8+ years of hands-on AMS verification experience in IP/SoC projects.
  • Proven track record in building verification environments using SystemVerilog, Verilog-AMS, or UVM.
  • Strong background in mixed-signal simulation and behavioral modeling.

Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

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