Chief Design Verification Engineer

2 days ago

Hyderabad, Telangana, India beBeeVerification Full time ₹ 15,00,000 - ₹ 22,50,000
Job Overview

We are seeking a highly skilled and motivated design verification engineer to join our team. The ideal candidate will be responsible for driving innovation and improving the quality of industry-leading technologies.

This is an excellent opportunity for someone who is passionate about modern processor architecture, digital design, and verification. The successful candidate will have excellent communication skills, experience collaborating with other engineers, and strong analytical and problem-solving skills.

Key Responsibilities:

  • Proficient in IP/Sub-System/SOC level ASIC verification
  • Debugging firmware and RTL code using simulation tools
  • Using UVM testbenches and working in Linux and Windows environments
  • Experienced with Verilog, System Verilog, C, and C++
  • Processor Micro-Architecture concepts Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Strong background in the C++ language, preferably on Linux with exposure to Windows platform
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
  • Good working knowledge of SystemC and TLM with some related experience
  • Scripting language experience: Perl, Ruby, Makefile, shell preferred
  • Exposure to leadership or mentorship is an asset
  • Desirable assets with prior exposure to video codec system or other multimedia solutions

Requirements:

  • Excellent communication and collaboration skills
  • Strong analytical and problem-solving skills
  • Experience with modern processor architecture and digital design
  • Proficient in multiple programming languages including Verilog, System Verilog, C, and C++

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