Lead Verification Specialist

5 days ago

Vijayawada, Andhra Pradesh, India beBeeVerification Full time ₹ 15,00,000 - ₹ 20,10,000
Senior Design Verification Engineer

We are seeking a seasoned professional with expertise in IP/SOC verification to join our team. As a Senior Design Verification Engineer, you will be responsible for developing and implementing testbenches using System Verilog/UVM.

The ideal candidate will have a strong background in functional verification of complex digital IPs and SoCs, as well as experience with processor-based SoC verification (e.g., RISC-V, ARM). They should also be proficient in bus protocols like AXI, AHB, APB, and have a good understanding of memory interfaces such as DDR/LPDDR.

This role involves working closely with RTL designers and system architects to ensure robust, high-quality silicon. The successful candidate will have excellent debugging skills using waveform viewers like Verdi, DVE, or Sim Vision, and familiarity with version control, scripting (Python/Perl/TCL), and simulation tools (e.g., VCS, Model Sim, Questa).

Key Responsibilities:
  • Develop and implement block-level and top-level testbenches using System Verilog/UVM.
  • Create detailed verification plans and drive the verification process from planning to coverage closure.
  • Verify IPs and SoC components including CPUs, memory controllers, interconnects, and custom logic.
  • Perform test case development, debugging, code coverage, and functional coverage analysis.
  • Drive regression infrastructure and manage automated test environments.
Required Skills & Experience:
  • Minimum 5 years of experience in IP/SOC functional verification.
  • Strong hands-on experience in System Verilog and UVM methodology.
  • Proficient in testbench architecture, test case development, and coverage-driven verification.
  • In-depth understanding of bus protocols like AXI, AHB, APB.
  • Experience with processor-based SoC verification (e.g., RISC-V, ARM).
Benefits:
  • Opportunity to work on complex digital IPs and SoCs.
  • Collaborative environment with experienced engineers.
  • Professional growth and development opportunities.
Others:

Familiarity with CI/CD pipelines and regression automation frameworks is a plus. Knowledge of cache systems, MMU, or peripheral subsystems is also desirable.

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