Lead System Architect for Next-Generation Interconnects

1 week ago

Tiruchi, Tamil Nadu, India beBeeLeadership Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Job Title

A leader in CPU Architecture and Logic design is sought after to drive the quantum revolution and AI era.

  • Responsible for the micro architecture, design, and development of high-bandwidth, low-latency on-chip interconnects.

Key Responsibilities

  • Design and architect different interconnect topologies driven by bandwidth, latency, and RAS requirements.
  • Develop features and present proposed architectures in High-Level Design discussions.
  • Develop micro-architecture, Design RTL, collaborate with Verification, DFT, Physical Design, FW, SW teams to develop features.
  • Sign-off Pre-silicon Designs meeting functional, area, and timing goals.
  • Participate in silicon bring-up and validation of hardware.

Requirements

  • At least 1 generation of processor interconnect design delivery leadership (e.g., UPI, AXI, AMBA, NoC).
  • Expertise in SMP coherency.
  • Experience in different on-chip interconnect topologies (e.g., mesh, crossbar).
  • Understanding of various snoop and data network protocols.
  • Understanding of latency & bandwidth requirements and effective means of implementation.
  • Working knowledge of queuing theory.
  • NUMA/NUCA architecture.
  • Proficient in HDLs - VHDL / Verilog.
  • Experience in high-speed and power-efficient logic design.
  • Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage.
  • Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design.
  • Experience in leading uarch, RTL design teams for feature enhancements.

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