Senior Analog Design Engineer for Next-Generation Silicon IP Solutions

2 weeks ago


India Mulya Technologies Full time
Overview

Mulya Technologies is at the forefront of accelerating critical data communication, empowering tomorrow's future with our DSP-based, multi-standard connectivity Silicon IP solutions.

Estimated Salary: ₹40,00,000 - ₹70,00,000 per annumJob Description

We are seeking a highly experienced Principal Analog Design Engineer to join our team in Bangalore. As a key member of our design team, you will be responsible for designing high-speed analog circuits, including DLLs, PLLs, and high-speed IO designs, as well as mentoring junior designers and supporting problem-solving efforts.

  • Design D2D/UCIe/HBM/DDR interface sub-blocks such as DLLs, PLLs, and high-speed custom logic designs.
  • Define block-level architecture and circuit topologies to meet system specifications.
  • Circuit design and simulation across PVT and sign-off quality matrix to meet specs.
  • Mentor junior designers and support them in problem-solving.
  • Support .lib generation and Verilog modeling for block-owned components and validate with schematic.
  • Custom layout guidelines and post-layout simulations.
  • Documentation, review, and sign-off on design.
Required Skills and Qualifications
  • Minimum 12 years of experience in analog circuit design from a reputed product-based company.
  • Experience in dual patterning FinFET design in TSMC 3nm, 5nm, 7nm, 16ffc, Samsung 3/5nm.
  • Experience designing circuits at 10-32 Gbps speed.
  • Understanding of device basics and physics, with knowledge of high-speed driver and receiver designs, PLL design with solid system understanding.
  • Hands-on experience of sub-block design of current mirrors, bandgap references, opamps, amplifiers with small-signal analysis of several topologies.
  • Proved track record of delivering high-speed, high-precision circuits for leading SoC designs.
  • Basic knowledge of layouts, including antenna checks, latchup issues, ESD constraints, ERC-related checks, matching, cross-talk, shielding, guard ring usage, LEF generation, .lib characterization, extraction setup, DRC LVS runs, switch knowledge, IR drop requirements, EM issues, parasitic matching, parasitic reduction techniques, and static and dynamic IR analysis.
  • Experience in ADC/DAC/regulator or high-speed SerDes circuit design.
  • B.Tech/M.Tech/MS in VLSI from a reputed university.
  • You will be reporting to Director Analog Design.
Benefits
  • Competitive Compensation Package.
  • Restricted Stock Units (RSUs).
  • Hybrid Working Model.
  • Provisions to pursue advanced education from premium institutes, eLearning content providers.
  • Medical Insurance and a cohort of wellness benefits.
  • Educational Assistance.
  • Advance Loan Assistance.
  • Office lunch & Snacks Facility.

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