
Senior System Verification Engineer
1 week ago
Role Summary:
We are seeking a skilled professional to spearhead system verification, focusing on processor and DSP subsystems. The ideal candidate will have extensive expertise in SystemVerilog and UVM, with hands-on experience in debug, performance analysis, and coverage closure.
Main Responsibilities:
- Develop and execute test cases and regressions for processor and DSP subsystems.
- Perform in-depth performance analysis for various workloads.
- Work on achieving comprehensive coverage, regressing, and debugging at the IP/Subsystem level.
- Collaborate closely with architecture, design, and software teams to drive project success.
- Design and implement C-based verification flows along with SV/UVM-based environments.
Required Skills and Qualifications:
- Strong expertise in SystemVerilog and UVM.
- C-based verification experience, particularly in processor systems.
- Familiarity with DSP architectures and Neural Network Engines (NNE).
- Proficiency in performance verification, including latency and throughput analysis.
- A minimum of 4 years of experience in IP/Subsystem DV.
Additional Requirements:
- End-to-end Debug Subsystem Verification, encompassing trace, crash debug, and visibility fabric.
- Development and execution of Verification Plans (VPlan).
- RTL DV, GLS, regression automation, and coverage closure expertise.
- Collaboration with SW and Architecture teams for debug feature validation.
- Support for ARM CPU debug infrastructure verification (CoreSight).
- Strong understanding of SystemVerilog, UVM, RTL DV, and GLS.
- Familiarity with ARM CoreSight Debug Architecture.
- ARM CPU debug methodologies, including trace and crash debug.
- Excellent knowledge of C programming and scripting languages (Python/Perl).
- A minimum of 4 years of relevant verification experience.
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