DFT Architect

3 days ago

Vadodara, Gujarat, India beBeeDigitalFaultTolerance Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

Job Overview

We are seeking a seasoned DFT professional to lead the development and implementation of Digital Fault Tolerance architecture with a focus on Memory Built-In Self-Test (MBIST) for advanced System-on-Chip (SoCs).

The ideal candidate will have hands-on experience in DFT planning, insertion, simulation, and pattern generation, as well as expertise in Automatic Test Pattern Generation (ATPG), SCAN, and MBIST.

This role requires collaboration with cross-functional teams throughout the design cycle to ensure high coverage and test quality in scan and MBIST.

Key Responsibilities:

  • DFT Planning and Implementation: Develop and implement Digital Fault Tolerance architecture with a focus on MBIST for SoCs.
  • ATPG and SCAN Expertise: Have in-depth knowledge of ATPG, SCAN, and MBIST, including tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent.
  • Memory Test Algorithms and Repair Analysis: Experience with memory test algorithms, repair analysis, and pattern generation.
  • Cross-Functional Collaboration: Work closely with RTL, Physical Design, and Verification teams to ensure seamless integration and high-quality results.

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