
Senior Verification Engineer Role
1 week ago
The successful candidate will oversee the development and execution of verification strategies for analog/mixed-signal IPs and SoCs. This includes designing and implementing verification plans, creating SystemVerilog, Verilog-AMS, or UVM-based verification environments, and performing co-simulation of analog/digital designs.
- Develop and execute comprehensive AMS verification strategies for analog/mixed-signal IPs and SoCs.
- Design and implement verification plans, including testbenches, stimulus generation, and checking strategies.
- Create and maintain SystemVerilog, Verilog-AMS, or UVM-based verification environments.
- Perform co-simulation of analog/digital designs using industry-standard tools.
- Collaborate with analog designers to create AMS behavioral models for early integration and verification.
- Debug complex AMS simulation issues across multiple abstraction levels.
- Drive coverage analysis and sign-off using functional, formal, and assertion-based methods.
Required Skills and Qualifications:
- Minimum 8+ years of hands-on experience in AMS verification for IP/SoC projects.
- Proven track record in building verification environments using SystemVerilog, Verilog-AMS, or UVM.
- Strong background in mixed-signal simulation and behavioral modeling.
Desirable Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
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