Lead RTL Design Engineer
2 days ago
We are seeking a seasoned Principal Design Engineer to join our team in developing high-quality RTL designs for Cadence's interface controller IP solution.
The ideal candidate will have experience in designing and supporting the RTL of PCIe/CXL/IDE/UALink IP solutions, working with existing teams, and ensuring compliance with LINT and CDC design guidelines.
- Develop and support RTL designs for the PCIe/CXL/IDE/UALink IP solution.
- Collaborate with the existing RTL team to add new features and ensure various customer configurations are clean as part of verification regressions.
- Support customers and ensure design cleanliness for LINT and CDC design guidelines.
Key Requirements:
- BE/BTech/ME/MTech in Electrical / Electronics / VLSI with experience as a design and verification engineer.
- 8-16 years of core RTL Design experience using Verilog.
- System Verilog experience and UVM-based environment usage/debugging required.
- PCIe/CXL/IDE experience needed, prior experience in complex protocol implementation a must.
- IP development team experience an advantage.
Desirable Skills:
- Scripting knowledge beneficial.
About the Role
This is an exciting opportunity to work on cutting-edge technology and contribute to the development of innovative RTL solutions. If you are a motivated and experienced design engineer looking for a challenging role, we encourage you to apply.
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