
Advanced Verification Professional
3 days ago
We are seeking a skilled System Verification Engineer to join our team. This is an exciting opportunity to work on cutting-edge projects and contribute to the development of innovative technologies.
Key Responsibilities:
- Develop, debug, and own SystemVerilog UVM-based testbenches for modem subsystems.
- Define test plans from specs and drive testcase implementation end-to-end.
- Perform RTL and netlist (gate-level) verification.
- Run regressions, analyze failures, and ensure functional & code coverage closure.
- Collaborate with design and verification leads for issue resolution.
Requirements:
- 7+ years of hands-on experience in SV UVM verification.
- Strong ownership in modem/IP verification (4G/5G preferred).
- Experience in writing testcases from spec and driving regressions.
- Expertise in both RTL and gate-level simulation.
- Good debugging and scripting (Python/Perl) skills.
Nice to Have:
- Knowledge of wireless protocols (LTE/5G).
- Experience with functional coverage closure.
- Exposure to DFT/low-power verification is a plus.
Benefits:
- Achieve 90% or higher functional coverage.
- Drive continuous improvement of the testbench architecture.
- Collaborate effectively with cross-functional teams.
Other Opportunities:
- Opportunities for growth and professional development.
- Competitive compensation package.
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