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Senior Physical Design Engineer
3 weeks ago
Job Description:
We are seeking a highly skilled Senior Physical Design Engineer to lead our team in delivering complex physical design projects. The successful candidate will be responsible for all aspects of physical design, including floorplanning, placement, budgeting, clock tree planning and analysis, scan re-ordering, and routing.
Key Responsibilities:
- Responsible for leading all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.
- Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.
- Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow.
- Experienced in design automation.
- Understanding of Timing constraints, SI prevention, Power reduction.
- Must have prior experience with Synopsys/Cadence/Mentor place and route tools.
- Must have completed design in 16nm and or 7nm.
- Proficient in Unix/TCL/Perl.
- Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability.
Requirements:
- 6+ years experience in ASIC physical design
- Experience with block implementation, extraction, timing and or full-chip designs
- Strong communication skills
- Strong hands-on TCL/Perl development skills
- Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project
- Track record of taping out complex chips on advanced process nodes