Digital Verification Engineer

3 weeks ago

Hyderabad, Telangana, India Analog Devices Full time

Job Summary

As a Digital Verification Engineer at Analog Devices, you will play a crucial role in the development of our cutting-edge verification methodologies. Your primary responsibility will be to design and implement verification strategies for complex microprocessor designs, neural networks, and high-speed peripherals. This involves creating UVM testbench architectures, developing DV flows, and defining test plans and methodologies for block, subsystem, and chip-level verification.

Key Responsibilities

  • Develop and implement verification strategies for complex SOC and IP designs
  • Create UVM testbench architectures and develop DV flows
  • Define test plans and methodologies for block, subsystem, and chip-level verification
  • Work with the design team to generate and review test plans and ensure closure of code and functional coverage
  • Collaborate with other verification team disciplines to determine correct functionality
  • Formal verification of IPs and subsystems
  • NOC, Interconnect verification
  • Performance verification and performance analysis of complex SOCs and end-to-end scenarios
  • System-level use case scenario definition, coding, and verification
  • Innovate verification solutions to meet deliverable schedules

Requirements

  • B.Tech/M.Tech with 2+ years of industry experience in Digital Pre-Silicon verification
  • Good understanding of SOC and subsystem design concepts and design architectures
  • Hands-on experience in developing, updating, and debugging Verilog, SV-UVM, and SOC-level testbenches
  • Experience in closing verification of block, subsystem-level verification using industry-standard metrics like code and functional coverage
  • Expertise in NOC, Bus, and Interconnect Verification. Coverage Analysis and improvements
  • Test Bench, TB, environment architect, and implement verification flow and methodology
  • Power-aware verification with UPF, Power analysis, and Power optimization
  • Knowledge of Formal verification is an added advantage
  • Gate-level simulation with timing-annotated
  • Strong knowledge of test-plan generation, coverage analysis, transaction-level modeling, pseudo, and constrained random techniques with System Verilog
  • In-depth knowledge of SV-UVM and debugging of testbenches is a must
  • Assertion and formal knowledge is an advantage
  • Knowledge of microprocessor cores such as ARM, RISC-V, Tensilica, Neural Network, GPU Cores is a plus
  • System Verilog, C/C++, System C, TCL/Python/shell-scripting
  • Exceptional interpersonal and communication skills
  • Quick to adopt new technologies with good problem-solving skills

Job Type

Experienced

Travel

No

Shift Type

1st Shift/Days

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