Senior Hardware Verification Engineer

1 week ago

Bengaluru, Karnataka, India beBeeDftspecialist Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Job Summary

The ideal candidate for this position will be responsible for implementing hardware Memory BIST features that support ATE, in-system test, debug and diagnostics needs of the memories in design.

Key Responsibilities:
  • Implementing MBIST features to support ATE, in-system test, debug and diagnostics needs of memories in design.
  • Collaborating with cross-functional teams to integrate and validate test logic throughout all phases of design and backend implementation flow.
  • Designing and debugging with minimal oversight.
  • Releasing high-quality patterns to the test team and supporting silicon bring-up and yield improvement.
Requirements:
  • 10+ years of experience as an ASIC Design DFT engineer with a broad mix of technologies.
  • Knowledge of latest trends in memory testing and silicon engineering.
  • Hands-on experience in JTAG & IJTAG protocols, MBIST and scan architectures.
  • Verification skills including System Verilog, LEC and validating test timing of design.
  • Experience working with gate-level simulations and debug with VCS and other simulators.
  • Understanding of testbench in System Verilog, UVM/VMM.
  • Post-silicon validation and debug experience, ability to work with ATE patterns.
  • Strong communication skills and ability to thrive in a dynamic environment.
  • Scripting skills: Python/Perl.

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