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High Speed Analog Design Engineer
2 months ago
We are a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. Our mission is to transform how the world uses information to enrich life.
Salary: $150,000 - $200,000 per year
About the Role
This is an equal opportunity position with excellent pay package for a highly skilled and challenging high speed PHY design team working on the latest technology nodes (12nm and below). The ideal candidate will take ownership of analog sub-blocks inside the PHY and drive the specification and implementation. This includes transistor and block level design, simulation, reliability and mixed mode simulations etc.
The selected candidate will also be responsible for driving layout of complex blocks through mask designers. They must conform to complex process rules as well as DFM. Participation in design reviews both internally and potentially with customers to explain design choices and robustness is also required. The candidate will work with people across multiple sites including overseas.
The successful candidate will help create IP EDA views: Behavioral/Verilog-A, timing views, abstract etc. Participation in silicon bring up, characterization, & correlations against models & simulations is also required. Mentorship and supervision of junior engineers is another key responsibility.
Required Skills and Qualifications
The ideal candidate should have circuit design experience in analog/mixed signal CMOS circuits in deep sub-micron technologies (5 – 40 nm) in High speed Memory interfaces (DDR3/4/5, LPDDR3/4x/5, GDDR5/6) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc). Prior experience in taking full ownership of at least one of the sub-blocks like PLL, DLL, CDR, high speed receiver with equalization, transmitter front end and high speed data path is necessary.
Candidate must have a deep understanding of analog and mixed signal circuit with experience in high speed link. Experience with TX RX Equalization (FFE/CTLE/DFE) is must. Experience with various CDR and Clocking architecture is also required. Candidate should have experience in finfet 10nm and below. Ability to create block level specification based on link budget and system level modeling using VerilogA/Python is essential.
Other key skills include strong fundamental knowledge for AMS design, Advanced CMOS and FinFet technologies. Understanding of Mismatch analysis & Monte-Carlo methodology/sims, transistor level Circuit level noise analysis. Understanding of device physics & deep-sub micron issues. Supervision of complex and/or sensitive analog layout and defining IP floorplan is also necessary.
Benefits
Mulya Technologies offers a competitive salary, excellent benefits package, and opportunities for growth and development. As an equal opportunity employer, we welcome applications from diverse candidates.
