Senior Digital Design Engineer

2 weeks ago

Bengaluru, Karnataka, India Analog Devices Full time
Job Title: Senior Engineer, Digital Design

At Analog Devices, we are seeking a highly skilled Senior Engineer, Digital Design to join our team. As a key member of our digital design team, you will be responsible for developing and implementing cutting-edge digital design solutions that meet the needs of our customers.

Key Responsibilities:
  • Collaborate with the Architecture team to develop detailed specifications, uArch, and development plans.
  • Design key digital blocks, such as accelerators and datapath IP, in Verilog and SystemVerilog, with built-in configurability to allow Power/Performance/Area tradeoffs.
  • Develop a strong understanding of heterogeneous processor cores and subsystems, including ARM, RISC-V, and DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, and SPU.
  • Develop user guides for RTL integration, synthesis, lint/CDC waivers, DFT, PnR, programming sequence, characterization, and other related tasks.
  • Evaluate 3rd party IPs on Power/Performance/Area (PPA) and other key qualitative aspects, such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration, and make recommendations.
  • Provide technical leadership and guidance to small teams of Micro-architects/RTL developers working on an SoC.
  • Work closely with the verification team for vPlan reviews and for complex debugs to resolve verification failures.
  • Participate in design specification, micro-architecture, and verification sign-off reviews.
  • Improve flows and methodologies to streamline IP development and integration.
  • Build development teams, including recruiting and interviewing.
Requirements:
  • Minimum B.E./B.Tech degree in Electrical/Electronics/Computer Science.
  • 5-8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog.
  • Strong understanding of control path and data-path digital design concepts with an eye for realizing correct-by-construction solutions.
  • Experience with specifying Design Verification (DV) requirements, such as test plans, coverage metrics, and evaluating DV quality to realize robust design quality.
  • Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis.
  • Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis.
  • Good interpersonal, teamwork, and communication skills to logically and effectively drive discussions with teams spread geographically.
  • Understanding of standard on-chip interfaces, such as APB/AHB/AXI/Stream protocols, is a strong plus.
  • Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus.
  • Experience with end-to-end ASIC/SoC product development and productization is very desirable.

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