Senior Front-End Silicon Design Engineering Manager

2 days ago

Bengaluru, Karnataka, India beBeeSilicon Full time ₹ 1,04,000 - ₹ 13,08,780

Job Title: Senior Front-End Silicon Design Engineering Manager

The role entails leading a team of experienced engineers to design and integrate front-end silicon IP in our SOC products. This involves driving RTL synthesis, PPA analysis, and ECO validations to improve QoR.

  • Main responsibilities include developing strategy, concepts, and scripting solutions for RTL synthesis, timing path analysis, and PPA analysis at the subsystem level.
  • Collaborate with the corporate methodology team to establish advanced FEINT methodologies and workflows.
  • Manage FEINT regression processes, create and improve FEINT workflows, processes, and quality metrics.

Required Skills and Qualifications:

  • A minimum of 10 years of relevant experience in FEINT engineering, preferably with strong technical leadership skills.
  • Familiarity with RTL design, synthesis, and ECO principles.
  • Proficiency in FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, Conformal, Formality, etc.
  • Excellent communication and problem-solving skills.

Benefits:

  • Opportunity to work on cutting-edge technologies and contribute to the development of high-performance IP.
  • Chance to lead a team of experienced engineers and develop their skills.
  • Professional growth and development opportunities.

Academic Credentials:

  • Masters Degree in Electrical Engineering, Computer Engineering, or Computer Science preferred.

Preferred Experience:

  • A strong understanding of RTL coding techniques for improved PPA-measured QoR.
  • Familiarity with RTL coding style for cleanness on design rule checks (LINT, CDC, RDC, etc.).

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