
Chief Digital System Verification Specialist
1 week ago
Key Responsibilities include thorough verification of complex digital systems. Verification engineers collaborate with cross-functional teams to identify and resolve functional failures.
- Develop and execute test plans, scripts, and methodologies for compliance with specifications and standards.
- Utilize expertise in System Verilog, UVM, and Digital Fundamentals to debug Netlist functional failures and Low Power Aware verification.
- Familiarity with Bus protocols like AHB/AXI/ACE/ACE-Lite and DDR families (LP/PC) and generations (DDR2/3/4/5).
Requirements:
- A minimum 3-5 years of experience in Design Verification is required.
- Hands-on experience in GLS, ZD/PAGLS/SDF/Scan dump verification is necessary.
- Strong understanding of Debug, UVM, System Verilog, and Digital Fundamentals is essential.
- The ability to debug Timing Simulation failure, setup and hold violation fundamentals is crucial.
Verification engineers must be able to work independently and as part of a team to achieve project goals. Effective communication and problem-solving skills are also necessary.
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