Senior FPGA System Validation Specialist

6 days ago


Hyderabad, Telangana, India beBeeValidation Full time ₹ 18,43,200 - ₹ 2,59,20,000
Job Description

As a System Integration and Validation Engineer, you will be responsible for owning integration and bring-up across FPGA and silicon EVBs for high-speed interfaces. The role is primarily focused on system/integration & validation (~80%) with some RTL design (~20%).

  • Key Responsibilities:
  • - FPGA Design Flow & Validation: Synthesis, P&R, timing closure (Vivado/Quartus); constraints (XDC/SDC); image generation and lab bring-up.
  • - RTL Design (20%): Targeted Verilog/SystemVerilog changes, glue logic, wrappers, and design-for-debug hooks.
  • - Interface Bring-up: PCIe, Ethernet, DDR4/5 & memory subsystemslink training, calibration, throughput/latency and margining.
  • - System-level Testing: Develop/execute test plans; corner, stress, and interoperability tests; performance and power characterization.
  • - Post-Silicon Validation: EVB setup, firmware/driver coordination, silicon feature enablement, errata reproduction and workarounds.
  • - Debugging: Board-level (oscilloscope, LA, protocol analyzers, JTAG) and design-level (waveforms, assertions, CDC/timing).
  • - Documentation & Reporting: Clear logs, defect reports, and release/readiness summaries; collaborate with procurement/installation for test assets.
Required Skills and Qualifications

- Strong RTL design/implementation (Verilog/SystemVerilog), hands-on FPGA flow and validation.
- Experience in system-level testing and post-silicon validation/bring-up.
- Proven debug skills at board and design levels; comfort with lab instruments and protocol analyzers.
- Familiarity with Xilinx (Vivado) and/or Intel (Quartus) toolchains.
- Working knowledge of PCIe, Ethernet, DDR4/5, memory protocols/subsystems.
- Scripting for productivity (TCL/Python/Bash); version control (Git).
- B.E./B.Tech/M.E./M.Tech in ECE/EE/CS or equivalent.

Benefits

30:60:90 Day Outcomes:
- 30d: FPGA sandbox up; first interface link-up with baseline measurements.
- 60d: Stable automated test runs; defects triaged with root-cause hypotheses.
- 90d: Multi-interface validation coverage; performance/power reports and sign-off criteria in place.

Interview Process

- Technical screen (RTL/FPGA/protocols)
- System & lab debug deep-dive
- Practical/log-based exercise
- Managerial fit.



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