Senior Digital Circuit Designer

2 weeks ago

Bengaluru, Karnataka, India beBeeDedicated Full time ₹ 25,00,000 - ₹ 40,00,000
Job Title:
Digital Circuit Design Expert

We are seeking a highly skilled Digital Circuit Design Expert to lead our team's digital circuit design efforts. The ideal candidate will have a strong background in digital circuit design and experience with Verilog and SystemVerilog.

The successful candidate will possess a solid understanding of top-level (SOC) level basic industry standard Arch knowledge, as well as expertise in SoC & IP level Integration, IPXACT, IORING, and Phys & GPIOs. This individual should also be familiar with design partitioning (tilification), clock domain crossing (CDC), reset domain crossing (RDC), LINT, VSI, UPF, LEC (Logic equivalence check), timing concepts, and SDC.

Additionally, the candidate should have proficiency in tools such as Vc_static, VC_spyglass LINT, CDC, and RDC, 0in, Formality, and Conformal LEC tool. The ideal candidate will also be proficient in design and scripting languages including Verilog, SV, Perl, Python, and TCL.

Key Responsibilities:
  • Coding knowledge for RTL
  • Top-level (SOC) level basic industry standard Arch knowledge
  • SoC & IP level Integration knowledge
  • IPXACT knowledge
  • IORING and Phys & GPIOs basic functionality
  • Design Partitioning(Tilification) knowledge
  • Design RTL quality checks:
    • Clock domain crossing(CDC)
    • Reset domain crossing(RDC)
    • LINT
    • VSI
    • UPF knowledge
    • LEC(Logic equivalence check)
    • Timing concepts & SDC knowledge
  • Tools knowledge:
    • Vc_static or equivalent other tools(VSI)
    • VC_spyglass LINT, CDC and RDC
    • 0in
    • Formality and conformal LEC tool
  • Design and scripting languages:
    • Verilog and SV
    • Perl
    • Python
    • TCL

Requirements:

  • Strong background in digital circuit design
  • Experience with Verilog and SystemVerilog
  • Solid understanding of top-level (SOC) level basic industry standard Arch knowledge
  • Expertise in SoC & IP level Integration, IPXACT, IORING, and Phys & GPIOs
  • Familiarity with design partitioning (tilification), clock domain crossing (CDC), reset domain crossing (RDC), LINT, VSI, UPF, LEC (Logic equivalence check), timing concepts, and SDC
  • Proficiency in tools such as Vc_static, VC_spyglass LINT, CDC, and RDC, 0in, Formality, and Conformal LEC tool
  • Proficient in design and scripting languages including Verilog, SV, Perl, Python, and TCL

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