Design Verification Engineering Lead

2 weeks ago

Bengaluru, Karnataka, India beBeeVerification Full time ₹ 30,00,000 - ₹ 50,00,000
Job Title: Design Verification Engineering Lead

We are seeking an experienced Design Verification Engineering Lead to contribute to the development and verification of advanced IP and SoC designs.

  • Create, execute, and debug test cases targeting high-speed protocol blocks.
  • Perform functional coverage analysis and assist in coverage closure.
  • Develop and maintain UVM-based and C/C++ testbenches for IP and SoC verification.

About the Role:

  • 6+ years of hands-on experience in functional verification (IP or SoC level).
  • Proficiency in System Verilog UVM methodology.
  • Familiarity with industry-standard simulators (VCS, Questa, XSIM, etc.).
  • Experience with scripting (Python, Perl, or Tcl) for automation.

Requirements:

  • Collaborate with RTL and architecture teams to define verification strategies and test plans.
  • Participate in code reviews, test reviews, and verification sign-off processes.
  • Exposure to at least one high-speed protocol: PCIe, USB 3.0, Ethernet, DDR, etc.

Key Responsibilities:

  • Lead a team of engineers in developing and verifying advanced IP and SoC designs.
  • Define verification strategies and test plans for complex digital systems.
  • Develop and maintain reusable verification components.

About Us:

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to product.

We are committed to delivering high-quality solutions that meet our customers' needs. Our team of experts works closely together to ensure seamless collaboration and effective communication throughout all stages of project execution.

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