Senior Physical Verification Engineer
2 weeks ago
We are Hiring a Senior Physical Verification Engineer for our client VLSI design services to the OEMs, ODMs & chipmakers Company located in Bangalore.
Key Responsibilities:
• Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
• Co-work with the Place & Route team to resolve full-chip layout integration issues.
• Coordinates with internal IP owners on IP related issues.
• Coordinates with the Manufacturing Team on DRC related issues.
• Provide automation solutions to improve efficiency in tape-out flow.
• Report on tapeout issues
Requirements:
• Bachelor/Masters Degree in Electrical/Electronic Engineering / Computer Science or equivalent
• With minimum 5 years of relevant experience
• Familiar with IC Design front-to-backend flow
• Preferably well-versed in Calibre ICV.
• Proficient in script programming, such as, Tcl, Perl or C-shell
• Proficient in UNIX (Linux) platforms
• Strong communication skills, problem solving and analytical skills
Mandatory skills:
• C-shell
• IC Design front-to-backend flow
• Tcl, Perl
• UNIX (Linux)
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