Principal Verification Specialist

2 weeks ago

Hyderabad, Telangana, India beBeeVerification Full time ₹ 10,05,000 - ₹ 20,10,000

Our company is seeking an experienced Senior Design Verification Engineer to join our team.

Key Responsibilities:

  • Understanding business requirements and functional specifications of IPs, subsystems, and SOC involves identifying key performance indicators and developing verification strategies to meet established goals.
  • The creation of a verification environment architecture document requires detailed planning and coordination with cross-functional teams.
  • Reviewing and revising design to meet agreed-upon acceptance criteria involves collaborating with engineers and stakeholders to ensure the final product meets customer expectations.
  • Developing code in System Verilog, UVM, and C for unit, subsystem, and SOC level verification requires expertise in software development and testing methodologies.
  • Performing RTL simulations using Synopsys and Cadence simulators involves executing test plans and analyzing results to identify areas for improvement.
  • Debugging and resolving problems found by simulations requires strong analytical and problem-solving skills.
  • Development of transactors, monitors, and models for performance verification involves creating complex software systems that require meticulous testing and validation.
  • Implementing performance verification flow including monitoring, synchronization, reporting, and self-checking mechanisms requires expertise in software development and testing methodologies.
  • Providing full report of performance metrics and bottlenecks involves summarizing findings and presenting recommendations for improvement.
  • Tracking tickets and code releases using Bug Tracking tool and GIT involves maintaining accurate records and collaborating with teams to resolve issues.
  • Performing UPF based power aware simulations requires expertise in low-power design and verification methodologies.
  • Coding assertion and functional coverage bins in SVA involves creating complex software systems that require meticulous testing and validation.
  • Code and functional coverage closure requires collaboration with teams to ensure all requirements are met.
  • Preparing and conducting reviews of Verification Sign-off documents to ensure SOC tape-out quality involves collaborating with stakeholders to ensure the final product meets customer expectations.

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