
Silicon Architecture Specialist
1 day ago
The role of the ASIC RTL Design Engineer focuses on developing microarchitecture details and performing RTL development, debugging functional/performance simulations, and participating in synthesis, timing/power estimation, and FPGA/silicon bring-up.
\Minimum Qualifications- Bachelor's degree in Electrical/Computer Engineering or equivalent practical experience.
- 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience in ARM-based SoCs, interconnects, and ASIC methodology.
- Master's degree in Electrical/Computer Engineering.
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
- Experience with methodologies for low power estimation, timing closure, synthesis.
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform RTL development (SystemVerilog), debug functional/performance simulations.
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
- Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.
- Communicate and work with multi-disciplined and multi-site teams.
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