Senior Digital Fault Tolerant Architect

6 days ago

Kozhikode, Kerala, India beBeeDigitalFaultTolerance Full time ₹ 8,00,000 - ₹ 12,10,000

Digital Fault Tolerant Architect

  • Develop and implement DFT architecture for ASIC/SoC designs to ensure seamless integration of digital fault tolerant features.
  • Collaborate with design teams to create robust digital fault tolerant solutions.
  • Analyze and optimize test patterns using ATPG tools for stuck-at, transition, and path delay faults.
  • Promote continuous improvement in test quality through fault simulation and coverage analysis.
  • Support silicon bring-up and debug of test-related issues to meet customer requirements.

We are seeking a talented individual who can work collaboratively with our cross-functional teams to deliver high-quality digital fault tolerant solutions.

Requirements:

  • Experience in developing DFT architecture for ASIC/SoC designs.
  • Strong understanding of digital fault tolerant principles and practices.
  • Ability to analyze and optimize test patterns using ATPG tools.
  • Familiarity with fault simulation and coverage analysis techniques.
  • Excellent communication and collaboration skills.

Benefits:

  • Competitive salary and benefits package.
  • Opportunities for career growth and professional development.
  • Collaborative and dynamic work environment.

Other:

  • We value diversity and inclusion in the workplace.
  • We offer flexible work arrangements to support work-life balance.
  • We prioritize employee well-being and mental health.

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