Memory Compiler Expert

11 hours ago

Surat, Gujarat, India beBeeSenior Full time ₹ 25,00,000 - ₹ 30,00,000

Job Opportunity: Senior Design Engineer

We are seeking a highly skilled Senior Design Engineer to join our team. As a key member, you will play a pivotal role in developing innovative memory compilers and fast cache instances for next-generation cores.

The ideal candidate possesses a deep understanding of computer architecture concepts and expertise in SRAM architecture, critical path modeling, full cut analysis, and Monte Carlo simulations.

In addition to strong technical skills, the successful candidate should have excellent design verification experience, including sense amplifier analysis, self-time analysis, and marginality analysis.

A solid grasp of high-speed/low-power CMOS circuit design, clocking schemes, static logic circuits, and complex logic circuits is also crucial.

The engineer will be responsible for leading a small team of designers in memory design, ensuring the development of digital circuits for memory blocks like SRAM, register files, and caches.

To succeed in this role, you must have minimum 7 years of experience in SRAM/memory design margin, char, and related quality checks. Experience with Cadence or Synopsys flows, circuit simulation, and optimization of standard cells is a plus.

Key Responsibilities:
  • Design and develop digital circuits for memory blocks
  • Perform simulations and verification to ensure functionality and optimize for power, performance, area, timing, and yield
Requirements:
  • Strong knowledge of physical implementation impact on circuit performance
  • Good understanding of high-performance and low-power circuit designs with exposure to FinFet technologies and bitcell stability analysis
  • Proven experience as the designated responsible individual for a memory design, leading a small team of designers
  • Good interpersonal skills
Nice to Have Skills and Experience:
  • Experience working on Cadence or Synopsys flows
  • Experience with circuit simulation and optimization of standard cells

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