Design Verification Engineering Leader
1 week ago
The position of Senior Design Verification Engineer entails developing comprehensive test plans and executing code in assembly, C++, and UVM. Maintaining UVM test bench components and debugging regression failures are also essential responsibilities.
Key Responsibilities:- Developing test plans and coding using UVM, Verilog, and System Verilog.
- Writing readable, maintainable, and verifiable code in UVM, SV, and digital design concepts.
- Debugging complex issues and optimizing code for performance.
- Hands-on experience with assembly, UVM, SV, and C++ programming languages.
- Experience in developing complex test benches/models in UVM, Verilog, and System Verilog.
- Knowledge of DPI interface, Ruby/Perl script programming skills, and Power Management, Clock, Reset is a valuable asset.
As a Senior Design Verification Engineer, you will have the opportunity to work on challenging projects, collaborate with experienced professionals, and advance your career in verification engineering.
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Design Verification Engineers
1 week ago
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Bengaluru, Karnataka, India Capgemini Engineering Full timeLead and mentor a team of verification engineers.Define verification strategies and develop reusable testbenches using UVM/OVM.Drive coverage-driven verification with code coverage, functional coverage, and assertions.Perform Gate-Level Simulations (GLS) and AMS/Power-aware verification.Collaborate with design, architecture, and validation teams.Automate...
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Bengaluru, Karnataka, India Capgemini Engineering Full timeJob DescriptionExperience: 5+yearsLocation: BangaloreJob Description:- You will be part of the team verifying IPs and SoCs leading to first Si success.- Manage and lead a team of Verification engineers- IP verification is coverage driven using latest industry standard methodologies and HVLs.- Work involves defining verification strategy, writing test plans,...
