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3 days ago
Job Title: Senior Design Verification Engineer
About the RoleWe are seeking an experienced Design Verification Engineer to join our team. The ideal candidate will have a strong background in IP and SoC-level verification, along with specialization in one or more of the following areas: processor/microarchitecture verification, high-speed interfaces (e.g., PCIe, USB, DDR), or GLS (Gate-Level Simulation).
The successful candidate will be responsible for ownership of verification strategy, planning, and execution in pre-silicon environments using industry-leading tools and methodologies.
Key Responsibilities- Develop and execute detailed verification plans for IP blocks, subsystems, or SoCs.
- Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
- Write and maintain directed and constrained-random test cases.
- Perform GLS (Gate-Level Simulation) with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
- Verify processor cores or custom pipelines, including cache/memory subsystems, MMUs, and coherency.
- Validate high-speed protocols (e.g., PCIe Gen4/Gen5, USB 3.x, DDR3/4/5, LPDDR, CXL).
- Debug RTL and testbench issues using waveforms, logs, and assertions.
- Collaborate with RTL, DFT, STA, firmware, and post-silicon teams to drive quality and coverage closure.
- Analyze functional/code/line/branch/coverage metrics and drive closure.
- Audit regressions and result analysis using scripting languages (Python, Perl, Shell, Tcl).
- Contribute to methodology improvements, tool evaluation, and reusable IP verification components.
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