Senior Design Engineer

5 days ago

Bengaluru, Karnataka, India beBeeDigital Full time ₹ 25,00,000 - ₹ 35,00,000

Lead Digital Design Manager

 

The ideal candidate will lead the digital design process for complex systems, manage a team of engineers and ensure successful implementation.

Responsibilities:

  • RTL Architecture and Design: Lead the RTL design of digital systems including microprocessors, ASICs, FPGA designs and system-on-chip (SoC) components.
  • Team Leadership: Manage and mentor a team of engineers providing technical guidance, training and fostering a collaborative environment.
  • Design Specifications: Work closely with architects and hardware engineers to define design specifications ensuring performance, area and power requirements are met.
  • RTL Coding: Write and review high-quality RTL code in Verilog, SystemVerilog or VHDL focusing on scalability, reusability and modularity.
  • Design Validation: Lead the development of testbenches and collaborate with verification teams to ensure thorough verification using simulation, formal verification and coverage analysis.
  • Timing and Performance Optimization: Drive performance and timing closure by working with design and implementation teams to address critical paths and optimize the design for low power, high speed and minimal area.
  • Integration: Lead the integration of RTL design blocks into larger systems ensuring smooth handoffs between various teams including digital, analog and software teams.
  • Mentorship and Collaboration: Provide mentorship to junior engineers and collaborate with cross-functional teams to ensure the design meets all system requirements.
  • Documentation and Reporting: Ensure proper documentation of design flows methodology and processes including regular design reviews and progress reports.
  • Continuous Improvement: Drive continuous improvement in digital design methodologies best practices and tools staying up-to-date with the latest trends and technologies.

Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering Computer Engineering or related field.
  • 7+ years experience in digital design for complex systems with at least 3+ years leadership experience in managing teams and projects.
  • Expertise in Verilog, SystemVerilog or VHDL for RTL coding with strong understanding of digital design principles.
  • Proven experience designing and verifying large-scale SoC, ASIC or FPGA designs.
  • Strong understanding of digital design flow including synthesis place-and-route timing analysis and power optimization.
  • Experience with simulation and verification methodologies including UVM SV-based testbenches and coverage-driven verification.
  • Proficient in using EDA tools such as Cadence Synopsys Mentor Graphics or other digital design and verification tools.
  • Strong knowledge of timing analysis static timing analysis (STA) and power optimization techniques.
  • Excellent problem-solving and debugging skills with experience addressing complex design issues.
  • Strong communication skills with ability to articulate technical ideas clearly effectively to both technical and non-technical stakeholders.

Experience: 7 to 12 Years Location: Bangalore

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