Lead Engineer for Physical Design and Verification
18 hours ago
We are seeking a highly skilled Lead Engineer for Physical Design and Verification to join our team at ADROITEC SYSTEMS PVT LTD. This is an excellent opportunity to work on challenging projects and contribute to the growth of our organization.
Job DescriptionThe successful candidate will be responsible for leading all aspects of physical design including floor planning, place and route, clock tree synthesis, clock distribution, extraction, timing closure, power and signal integrity analysis, physical verification, and DFM. The ideal candidate must have participated in all stages of the design process and have a deep understanding of concepts related to synthesis, placement, routing, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure.
Requirements and Qualifications- Experience in full-chip physical design and verification
- Strong knowledge of EDA tools and scripting languages such as PERL, TCL, and Python
- Good understanding of lower tech node layout verification and experience with rule files
- Ability to take ownership of block/sub-system execution and lead cross-functional teams
- Excellent communication and project management skills
We offer a competitive salary range of approximately ₹1,200,000 - ₹1,800,000 per annum, depending on experience and qualifications. In addition to the base salary, we provide a comprehensive benefits package, including health insurance, retirement plan, and opportunities for professional growth and development.
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