Advanced Verification Engineer

13 hours ago


Kanpur, Uttar Pradesh, India beBeeEngineer Full time ₹ 20,00,000 - ₹ 25,00,000
Advanced Verification Engineer - Analog Mixed Signal

We are seeking an experienced Advanced Verification Engineer to lead the planning, development, and execution of AMS verification strategies for analog/mixed-signal IPs and SoCs.

  • Main Responsibilities:
  • Verification Planning: Develop and implement comprehensive verification plans, including testbenches, stimulus generation, and checking strategies.
  • Verification Environment Development: Create and maintain SystemVerilog, Verilog-AMS, or UVM-based verification environments.
  • Cosimulation: Perform cosimulation of analog/digital designs using industry tools.
  • Mixed-Signal Simulations: Conduct mixed-signal simulations, behavioral modeling of analog blocks, and integration into top-level environments.
  • Collaboration: Work closely with analog designers to create AMS behavioral models (e.g., Verilog-A/AMS) for early integration and verification.
  • Issue Debugging: Troubleshoot complex AMS simulation issues across multiple abstraction levels.
  • Coverage Analysis: Drive coverage analysis and sign-off using functional, formal, and assertion-based methods.
  • Mentorship: Guide junior engineers in best practices, methodologies, and tool usage.
Requirements:
  • Experience: Minimum 8+ years of hands-on AMS verification experience in IP/SoC projects.
  • Skills: Proven track record in building verification environments using SystemVerilog, Verilog-AMS, or UVM.
  • Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.


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