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3 days ago
We are committed to accelerating next-generation computing experiences that transform lives. Our mission is to develop innovative products that address the world's most critical challenges.
The RoleAs a Senior Silicon Design Engineer, you will be responsible for deploying group-specific flow deployment for IP subsystems and SOC, collaborating with CAD teams and PD implementation teams for synthesis, LEC, CLP, STA, and PNR.
Key Responsibilities- Physical implementation flow deployment for synthesis, LEC, CLP, STA, and PNR
- Collaborate with central CAD teams, DFX, EDA vendors, and design teams to achieve optimal Performance, Power, and Area (PPA)
- Deliver high-quality and bug-free flows for 2nm to 7nm technology nodes
- Debug and resolve technical issues in tools and flows
- Experience in CAD-based physical implementation workflows for synthesis, LEC, CLP, STA, and PNR
- Familiarity with automation using Perl, TCL, and Python programming languages
- Excellent communication and collaboration skills
- Understanding of RTL and DFT fundamentals
This role offers the opportunity to work on cutting-edge projects, collaborate with talented professionals, and contribute to the development of innovative products that make a meaningful impact.
Additional InformationA Bachelor's degree with 5 years of experience or a Master's degree with 3 years of experience in Electrical Engineering is required.
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