High-Level RTL Design Specialist
2 weeks ago
As a Senior ASIC Design Engineer at Modernize Chip Solutions (MCS), you will be responsible for leading the design of complex ASICs using Verilog. Your expertise in SoC and subsystem integration, including peripherals like PCIe, Ethernet, and USB, will be essential in bringing up the front-end flow environment. You will also be responsible for developing strong flows, lint, CDC, synthesis, formal verification, and VCLP, as well as creating Tcl or Perl scripts for constraint development, timing analysis, and signoff. Your extensive experience in RTL design, coupled with your outstanding technical skills, will be crucial in driving our design initiatives forward. We are seeking a highly motivated and experienced professional to join our team and contribute to the growth and success of MCS.
Requirements:
Total Years of Experience: 10+ Yrs
Hands-on RTL Design using Verilog
SoC and Subsystem integration, Peripherals like PCIe, Ethernet, and USB Integration
Front-end flow environment bring-up
Strong in Flows, Lint, CDC, Synthesis, Formal Verification, VCLP
Tcl or Perl scripting knowledge
CDC and Synthesis constraint development, Timing analysis, Signoff
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