AI-Driven Chip Design Specialist

2 weeks ago

Ellore, Andhra Pradesh, India beBeeSynthesis Full time ₹ 16,00,000 - ₹ 32,00,000

At the forefront of semiconductor engineering, we're a startup driving innovation worldwide. Our engineers work on cutting-edge technology nodes and state-of-the-art designs in AI/ML, Datacenter, Automotive, and 5G domains.

  • We offer a unique opportunity for young engineers to showcase their abilities and experience globally from day one, while learning from industry leaders.

Eteros invests in our engineers' continuous learning and growth, enabling them to expand their knowledge breadth and depth, preparing them for fast-track career development and longevity.

As a Synthesis and Static Timing Analysis Staff Design Engineer/Design Manager, you'll lead synthesis, static timing, and DFT efforts for an advanced mixed-signal chip for a high-profile Silicon Valley company.

You'll be at the heart of the SoC design effort, interfacing with all disciplines and having critical impact in delivering functional products to customers quickly.

  • The position requires thorough knowledge of ASIC design timing closure flow and methodology.
  • You'll be responsible for full-chip and block-level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).

You'll analyze timing reports, utilize scripting techniques to develop insights, and drive rapid timing closure.

What's in it for you:

  • Opportunity to work on leading-edge technologies
  • Career development and growth opportunities
  • Competitive compensation package
  • Medical benefits and more

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