
Senior Design Engineer for PnR Activities
1 week ago
Key Responsibilities:
• Perform IP/Block level Physical Design activities from Netlist to GDS-II.
• Possess strong knowledge of all Physical Design activities including Floor-planning, Placement, CTS, Routing, Timing closure and signoff checks like FEV, VCLP, EMIR and PV.
• Proficient in industry-standard EDA tools such as Synopsys, Cadence, and Mentor.
• Experienced in working with DSM technologies, particularly TSMC 5nm and below.
• Skilled in scripting languages.
Requirements:
• Minimum experience: 7+ years
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