Expert FPGA Designer and Engineer
10 hours ago
We are seeking a highly skilled individual to assume a key role in our engineering team.
Responsibilities:- The selected candidate will collaborate with design, synthesis, and physical design teams to ensure the integrity of digital fault tolerance (DFT) designs.
- They will work closely with manufacturing and validation teams to implement test strategies for prototype bring-up and ensure compliance with industry standards.
- The Technical Lead will be responsible for debugging and optimizing DFT networks to achieve minimal test times while ensuring quality and reliability.
- Evaluation and integration of latest DFT tools and methodologies with EDA vendors is also expected from the successful candidate.
- At least 15 years of experience in DFT architecture and implementation.
- Strong expertise in FPGA-based DFT methodologies (Xilinx, Intel/Altera, Lattice, etc.) is essential.
- Proficiency in Verilog/VHDL for FPGA design and test logic implementation is required.
- Hands-on experience with DFT tools (Synopsys DFT Compiler, Tessent, Mentor Tessent, Cadence Modus, or similar) is necessary.
- Strong knowledge of JTAG (IEEE 1149.1, 1149.6), scan insertion, ATPG, MBIST, LBIST, and fault modeling is crucial.
- Experience in timing analysis and synthesis-aware DFT implementation is desirable.
- Familiarity with FPGA prototyping and board bring-up is an asset.
- Hands-on scripting skills in Python, TCL, Perl, or Shell for DFT automation are expected.
- Experience in AI/ML-driven DFT automation would be beneficial.
- Knowledge of high-speed interfaces and SERDES testing would be an asset.
- Experience with post-silicon validation and Automated Test Equipment (ATE) would be valuable.
- Strong debugging skills using logic analyzers, oscilloscopes, and FPGA tools would be an advantage.
This is a unique opportunity to work on cutting-edge FPGA-based designs for high-performance computing, automotive, or AI applications.
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