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1 week ago
We are seeking a skilled Digital Verification Specialist to work on complex digital circuits.
The ideal candidate will have a strong background in verification and synthesis, with a focus on Gate Level Synthesis (GLS).
- Verilog/SystemVerilog: Proficiency in writing and verifying digital circuits using these languages.
- SDF Concepts: Understanding of Static Data Flow (SDF) concepts and their application in verification.
- EDA Tools: Familiarity with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, and Mentor Questa.
- Timing Analysis, synthesis, and place & route (PnR) flow: Understanding of the timing analysis process, synthesis, and place & route flow in digital design.
- X-checking, reset verification, and glitches in gate-level simulation: Experience in handling x-checking, reset verification, and glitches in gate-level simulation.
- Debugging and Problem-Solving: Strong debugging and problem-solving skills to identify and resolve complex issues in verification.
- Scripting Skills: Proficiency in scripting languages such as Perl, Python, TCL, or Shell.
A successful candidate will possess excellent communication and teamwork abilities, with the capacity to collaborate effectively with cross-functional teams to drive project success.
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