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The role of a Senior Digital Verification Engineer at AMD is to plan, build, and execute the verification of new and existing features for AMD's CSoC DV. This involves ensuring that the final design has no bugs.

You will be part of a team that focuses on digital design and verification. As a team player with excellent communication skills, you will collaborate with other engineers located in different sites/timezones. Your strong analytical and problem-solving skills will be essential in developing complex verification environments using the latest coverage/assertions based verification design methodology.

  • Participate in pre-silicon verification for full chip, blocks, multi-chip, and system-level verification
  • Specify and own design verification plans at SOC level/IP level
  • Collaborate with architects, hardware engineers, and firmware engineers to understand new features to be verified
  • Develop complex verification environments using the latest coverage/assertions based verification design methodology

To succeed in this role, you will need:

  • Minimum 8+ years of experience in ASIC Design Verification
  • Excellent knowledge of ASIC Design Flow and SOC architecture
  • Experience in developing complex testbenches/models in Verilog, SystemVerilog, or SystemC
  • Experience with coverage-based verification methodology
  • Excellent debug skills in functional simulations